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Data Structures | |
| struct | STG_STRUCT |
| union | IO32 |
| union | LONGBYTE |
| union | WORDBYTE |
Defines | |
| #define | __attribute__(x) |
| #define | DEFAULT_STG_BASE_ADDRESS 0x200 |
| #define | STG_SUCCESS 0 |
| #define | STG_FAILURE 1 |
| #define | NUM_AXIS_IN_SYS 8 |
| #define | MAX_AXIS 8 |
| #define | CNT0_D 0x00 |
| #define | CNT1_D 0x01 |
| #define | CNT0_C 0x02 |
| #define | CNT1_C 0x03 |
| #define | CNT2_D 0x04 |
| #define | CNT3_D 0x05 |
| #define | CNT2_C 0x06 |
| #define | CNT3_C 0x07 |
| #define | CNT4_D 0x08 |
| #define | CNT5_D 0x09 |
| #define | CNT4_C 0x0a |
| #define | CNT5_C 0x0b |
| #define | CNT6_D 0x0c |
| #define | CNT7_D 0x0d |
| #define | CNT6_C 0x0e |
| #define | CNT7_C 0x0f |
| #define | DAC_0 0x10 |
| #define | DAC_1 0x12 |
| #define | DAC_2 0x14 |
| #define | DAC_3 0x16 |
| #define | DAC_4 0x18 |
| #define | DAC_5 0x1a |
| #define | DAC_6 0x1c |
| #define | DAC_7 0x1e |
| #define | ADC 0x410 |
| #define | ADC_0 0x410 |
| #define | ADC_1 0x412 |
| #define | ADC_2 0x414 |
| #define | ADC_3 0x416 |
| #define | ADC_4 0x418 |
| #define | ADC_5 0x41a |
| #define | ADC_6 0x41c |
| #define | ADC_7 0x41e |
| #define | CNTRL0 0x401 |
| #define | DIO_A 0x400 |
| #define | DIO_B 0x402 |
| #define | DIO_C 0x404 |
| #define | DIO_D 0x401 |
| #define | PORT_A 0x400 |
| #define | PORT_B 0x402 |
| #define | PORT_C 0x404 |
| #define | PORT_D 0x405 |
| #define | INTC 0x405 |
| #define | BRDTST 0x403 |
| #define | MIO_1 0x406 |
| #define | ABC_DIR 0x406 |
| #define | MIO_2 0x407 |
| #define | D_DIR 0x407 |
| #define | ODDRST 0x407 |
| #define | TIMER_0 0x408 |
| #define | TIMER_1 0x40a |
| #define | TIMER_2 0x40c |
| #define | TMRCMD 0x40e |
| #define | ICW1 0x409 |
| #define | ICW2 0x40b |
| #define | OCW1 0x40b |
| #define | OCW2 0x409 |
| #define | OCW3 0x409 |
| #define | IRRreg 0x409 |
| #define | ISR 0x409 |
| #define | IDLEN 0x409 |
| #define | IMR 0x40b |
| #define | SELDI 0x40b |
| #define | IDL 0x40d |
| #define | CNTRL1 0x40f |
| #define | IXEVN 0x80 |
| #define | IXODD 0x40 |
| #define | LIXEVN 0x20 |
| #define | LIXODD 0x10 |
| #define | EOC 0x08 |
| #define | TP0 0x04 |
| #define | USR_INT 0x02 |
| #define | TP2 0x01 |
| #define | AUTOZERO 0x80 |
| #define | IXLVL 0x40 |
| #define | IXS1 0x20 |
| #define | IXS0 0x10 |
| #define | USRINT 0x08 |
| #define | IA2 0x04 |
| #define | IA1 0x02 |
| #define | IA0 0x01 |
| #define | CNTRL0_AZ 0x80 |
| #define | CNTRL0_AD2 0x40 |
| #define | CNTRL0_AD1 0x20 |
| #define | CNTRL0_AD0 0x10 |
| #define | CNTRL0_CAL 0x08 |
| #define | CNTRL0_IA2 0x04 |
| #define | CNTRL0_IA1 0x02 |
| #define | CNTRL0_IA0 0x01 |
| #define | CNTRL1_WDTOUT 0x80 |
| #define | CNTRL1_INT_G2 0x40 |
| #define | CNTRL1_INT_T0 0x10 |
| #define | CNTRL1_INT_T2 0x20 |
| #define | CNTRL1_NOT_SLAVE 0x08 |
| #define | CNTRL1_IEN_G2 0x04 |
| #define | CNTRL1_IEN_T0 0x01 |
| #define | CNTRL1_IEN_T2 0x02 |
| #define | BRDTST_EOC 0x08 |
| #define | INTR 13 |
| #define | INT_MASK 0x20 |
| #define | IC_ADD 0x20 |
| #define | EOI_5 0x65 |
| #define | IC_MASK 0x21 |
| #define | IRQSL 0x84 |
| #define | STG_PORT_A 0x01 |
| #define | STG_PORT_B 0x02 |
| #define | STG_PORT_C_LO 0x04 |
| #define | STG_PORT_C_HI 0x08 |
| #define | STG_PORT_C (STG_PORT_C_LO | STG_PORT_C_HI) |
| #define | STG_PORT_D_LO 0x10 |
| #define | STG_PORT_D_HI 0x20 |
| #define | STG_PORT_D (STG_PORT_D_LO | STG_PORT_D_HI) |
| #define | STG_PORT_INPUT 0 |
| #define | STG_PORT_OUTPUT 1 |
| #define | A_DIR_BIT 0x10 |
| #define | B_DIR_BIT 0x02 |
| #define | C_LOW_DIR_BIT 0x01 |
| #define | C_HI_DIR_BIT 0x08 |
| #define | D_DIR_BIT 0x10 |
| #define | D_LOW_DIR_BIT 0x01 |
| #define | D_HI_DIR_BIT 0x08 |
| #define | _500_MICROSECONDS 500 |
| #define | _1_MILLISECOND 1000 |
| #define | _2_MILLISECONDS 2000 |
| #define | _3_MILLISECONDS 3000 |
| #define | _4_MILLISECONDS 4000 |
| #define | _5_MILLISECONDS 5000 |
| #define | _10_MILLISECONDS 10000 |
| #define | _100_MILLISECONDS 100000L |
| #define | _1_SECOND 1000000L |
| #define | MAX_PERIOD -1L |
| #define | NO_BOARD 1 |
| #define | BOARD_PRESENT 0 |
| #define | MODEL_NO_ID 0 |
| #define | MODEL1 1 |
| #define | MODEL2 2 |
Enumerations | |
| enum | ePort_typ { A_port, B_port, C_port, D_port } |
| enum | eHomeDir_typ { HomeSwitchFORWARD, HomeSwitchREVERSE } |
Functions | |
| char | __attribute__ ((unused)) stg_h[]="$Id |
| void | ServoToGoConstructor (STG_STRUCT *stg, unsigned short wRequestedIrq) |
| void | ServoToGoDestructor (STG_STRUCT *stg) |
| void | Initialize (STG_STRUCT *stg, unsigned short wRequestedIrq) |
| void | SetIrq (STG_STRUCT *stg, unsigned short wRequestedIrq) |
| unsigned short | BaseFind (STG_STRUCT *stg) |
| unsigned short | BrdtstOK (STG_STRUCT *stg, unsigned short wBaseAddress) |
| void | SetDDir (STG_STRUCT *stg, unsigned short nSwDir) |
| void | MotSim (STG_STRUCT *stg) |
| void | RawDAC (STG_STRUCT *stg, unsigned short nAxis, long lCounts) |
| void | StartADC (STG_STRUCT *stg, unsigned short wAxis) |
| short | SpinReadADC (STG_STRUCT *stg, unsigned short wAxis) |
| long | ReadADC (STG_STRUCT *stg, unsigned short wAxis, short *counts) |
| void | AutoZeroAdc (STG_STRUCT *stg) |
| void | DontAutoZeroAdc (STG_STRUCT *stg) |
| void | CalADC (STG_STRUCT *stg) |
| void | EncoderInit (STG_STRUCT *stg) |
| void | EncoderLatch (STG_STRUCT *stg) |
| void | EncoderResetAddr (STG_STRUCT *stg) |
| void | SetEncoderCounts (STG_STRUCT *stg, unsigned short nAxis, long lCounts) |
| void | SelectIndexAxis (STG_STRUCT *stg, unsigned char byAxis, unsigned char byPol) |
| void | SelectIndexOrExtLatch (STG_STRUCT *stg, unsigned char bySelectBits) |
| void | EnableCounterLatchOnIndexOrExt (STG_STRUCT *stg, unsigned char bySelectBits) |
| short | IndexPulse (STG_STRUCT *stg) |
| unsigned short | IndexPulseLatch (STG_STRUCT *stg) |
| void | ResetIndexLatches (STG_STRUCT *stg, unsigned char byLatchBits) |
| unsigned char | CurrentIRR (STG_STRUCT *stg) |
| void | ResetIndexLatch (STG_STRUCT *stg) |
| unsigned char | GetIndexLatches (STG_STRUCT *stg) |
| unsigned char | GetSELDI (STG_STRUCT *stg) |
| unsigned char | GetIDLEN (STG_STRUCT *stg) |
| unsigned char | GetCNTRL0 (STG_STRUCT *stg) |
| unsigned char | GetCNTRL1 (STG_STRUCT *stg) |
| unsigned char | GetBRDTST (STG_STRUCT *stg) |
| void | ResetWatchdogLatch (STG_STRUCT *stg) |
| void | EncReadAll (STG_STRUCT *stg, LONGBYTE *lbEnc) |
| unsigned long | RawDI (STG_STRUCT *stg) |
| void | RawDO (STG_STRUCT *stg, unsigned long lOutBits) |
| void | RawDOPort (STG_STRUCT *stg, unsigned char byBitNumber, unsigned char bySet0or1, unsigned short nPort) |
| void | DioDirection (STG_STRUCT *stg, const unsigned short nSwDir) |
| void | StopTimer (STG_STRUCT *stg) |
| void | StartInterrupts (STG_STRUCT *stg) |
| void | IrqReset (STG_STRUCT *stg) |
| void | SelectInterruptPeriod (STG_STRUCT *stg, long lPeriodSelect) |
| void | StopInterrupts (STG_STRUCT *stg) |
| unsigned short | GetBoardPresence (STG_STRUCT *stg) |
| unsigned short | GetAxes (STG_STRUCT *stg) |
| unsigned short | GetIrq (STG_STRUCT *stg) |
| unsigned short | GetAddr (STG_STRUCT *stg) |
| unsigned short | GetModel (STG_STRUCT *stg) |
| void | Timer2Delay (STG_STRUCT *stg, unsigned short counts) |
| void | StartTimer2TerminalCount (STG_STRUCT *stg, unsigned short count) |
| void | StartTimer2RTI (STG_STRUCT *stg, unsigned short count) |
| unsigned short | ReadTimer2TerminalCount (STG_STRUCT *stg) |
| short | PollTimer2 (STG_STRUCT *stg) |
| void | MaskTimer2Interrupt (STG_STRUCT *stg) |
| void | UnMaskTimer2Interrupt (STG_STRUCT *stg) |
| int | AddressInRange (STG_STRUCT *stg, long) |
Variables | |
| eDir_typ | |
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Definition at line 242 of file stg2.h. 00242 { HomeSwitchFORWARD, HomeSwitchREVERSE } eHomeDir_typ;
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Definition at line 241 of file stg2.h. 00241 { A_port, B_port, C_port, D_port } ePort_typ;
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Definition at line 1377 of file stg_v2_axis8.c. 01378 {
01379 /* set the Analog to Digital converter to autozero on each conversion */
01380
01381 if (stg->wModel == MODEL1)
01382 fOutP(stg->wBaseAddress + INTC, fInP(stg->wBaseAddress + INTC) & ~AUTOZERO);
01383 else /* MODEL2 */
01384 fOutP(stg->wBaseAddress + CNTRL0, fInP(stg->wBaseAddress + CNTRL0) | CNTRL0_AZ);
01385 }
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Definition at line 355 of file stg_v2_axis8.c. 00356 {
00357 short i;
00358 unsigned short io_add;
00359
00360 for (i = 15; i >= 0; i--) /* search all possible addresses */
00361 {
00362 io_add = i * 0x20 + 0x200;
00363 if ( BrdtstOK(stg,
00364 io_add) )
00365 return io_add;
00366 }
00367 return(0);
00368 }
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Definition at line 378 of file stg_v2_axis8.c. 00379 {
00380 unsigned short BrdtstAddress;
00381 unsigned short SerSeq, HighNibble;
00382 int j;
00383
00384 BrdtstAddress = BaseAddress + BRDTST;
00385
00386 SerSeq = 0;
00387 for (j = 7; j >= 0; j--)
00388 {
00389 HighNibble = fInP(BrdtstAddress) >> 4;
00390 if (HighNibble & 8) /* is SER set */
00391 {
00392 /* shift bit to position specifed by Q2, Q1, Q0 */
00393 /* which are the lower three bits. Put bit in SerSeq. */
00394 SerSeq |= 1 << (HighNibble & 7);
00395 }
00396 }
00397 if (SerSeq == 0x75) /* SER sequence is 01110101 */
00398 {
00399 stg->wModel = MODEL1;
00400 return 1; /*true */
00401 }
00402 if (SerSeq == 0x74) /* SER sequence is 01110100 */
00403 {
00404 stg->wModel = MODEL2;
00405 return 1; /* true */
00406 }
00407 /* stg->wModel = MODEL_NO_ID; */
00408 return 0; /* false */
00409 }
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Definition at line 1397 of file stg_v2_axis8.c. 01398 {
01399 /* Start calibration cycle on ADC chip */
01400
01401 unsigned char Cntrl0;
01402
01403 if (stg->wModel == MODEL2) /* this function only in Model 2 board. */
01404 {
01405 Cntrl0 = fInP(stg->wBaseAddress + CNTRL0) & 0x07; /* save irq */
01406 fOutP(stg->wBaseAddress + CNTRL0, Cntrl0); /* cal is low */
01407 /* cal pulse should be 60 ns. The ISA bus is 10 MHz. or 100 ns. */
01408 /* so we can just set it back high. */
01409 fOutP(stg->wBaseAddress + CNTRL0, Cntrl0 | 0x08); /* cal is high */
01410 }
01411 }
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Definition at line 1077 of file stg_v2_axis8.c. 01078 {
01079 fOutP(stg->wBaseAddress + OCW3, 0x0a); /* IRR on next read */
01080 return fInP(stg->wBaseAddress + IRRreg);
01081 }
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Definition at line 1254 of file stg_v2_axis8.c. 01255 {
01256 unsigned char byHwDir; /* direction bits for hardware */
01257 unsigned long lCurrentData;
01258
01259 if (stg->wNoBoardFlag == NO_BOARD)
01260 {
01261 return;
01262 }
01263
01264 /* get the current data in the I/O ports. We'll replace it when we're */
01265 /* done. When you change a port to output, it will start at what the */
01266 /* input was (usually high). This way, bits won't change (except for a */
01267 /* glitch) when a port is set to output. */
01268
01269 lCurrentData = RawDI(stg);
01270
01271 byHwDir = 0x9b; /* initially all ports input */
01272
01273 if (nSwDir & STG_PORT_A) /* check the bit for A out */
01274 byHwDir &= ~A_DIR_BIT; /* if output, set bit to 0 */
01275 if (nSwDir & STG_PORT_B)
01276 byHwDir &= ~B_DIR_BIT;
01277 if (nSwDir & STG_PORT_C_LO)
01278 byHwDir &= ~C_LOW_DIR_BIT;
01279 if (nSwDir & STG_PORT_C_HI)
01280 byHwDir &= ~C_HI_DIR_BIT;
01281
01282 fOutP(stg->wBaseAddress + ABC_DIR, byHwDir); /* set direction for A, B and C */
01283
01284 SetDDir(stg, nSwDir);
01285 stg->wSaveDirs = nSwDir; /* save, mostly for other function */
01286 RawDO(stg, lCurrentData);
01287 }
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Definition at line 1387 of file stg_v2_axis8.c. 01388 {
01389 /* set the Analog to Digital converter to NOT autozero */
01390
01391 if (stg->wModel == MODEL1)
01392 fOutP(stg->wBaseAddress + INTC, fInP(stg->wBaseAddress + INTC) | AUTOZERO);
01393 else /* MODEL2 */
01394 fOutP(stg->wBaseAddress + CNTRL0, fInP(stg->wBaseAddress + CNTRL0) & ~CNTRL0_AZ);
01395 }
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Definition at line 1066 of file stg_v2_axis8.c. 01067 {
01068 /* routine for Model 2 */
01069 fOutP(stg->wBaseAddress + IDLEN, bySelectBits);
01070 }
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Definition at line 917 of file stg_v2_axis8.c. 00918 {
00919 WORDBYTE wbTransfer;
00920 /* static unsigned char byOldByte2[MAX_AXIS]; */
00921 /* static unsigned char byEncHighByte[MAX_AXIS]; */
00922 short i;
00923
00924 if (stg->wNoBoardFlag == NO_BOARD)
00925 {
00926 for (i = 0; i < 8; i++)
00927 {
00928 lbEnc[i].Long = stg->lSimEnc[i];
00929 }
00930 return;
00931 }
00932
00933 /* Disable interrupts here? No, the timer will latch new data in the */
00934 /* hardware anyway. Maybe we should stop the timer? In an interrupt */
00935 /* service routine, you're synchronized with the timer; so the readings */
00936 /* will never change while you're reading them. If you're polling, you */
00937 /* would first latch the encoder counts with the EncoderLatch() function. */
00938 /* But, the timer could latch the counts again, in the middle of the read. */
00939 /* A critical section will help in some extreme cases. */
00940
00941 /* reset counter internal addr ptr to point to first byte */
00942 /* BUG FIX-- don't go past 4 axes on 4 axis board */
00943 fOutPW(stg->wBaseAddress + CNT0_C, 0x0101);
00944 fOutPW(stg->wBaseAddress + CNT2_C, 0x0101);
00945 if (stg->wAxesInSys > 4) {
00946 fOutPW(stg->wBaseAddress + CNT4_C, 0x0101);
00947 fOutPW(stg->wBaseAddress + CNT6_C, 0x0101);
00948 }
00949
00950 for (i = 0; i < 3; i++) /* 24 bits means get 3 bytes each */
00951 {
00952 wbTransfer.Word = fInPW(stg->wBaseAddress + CNT0_D);
00953
00954 lbEnc[0].Byte[i] = wbTransfer.Byte.high;
00955 lbEnc[1].Byte[i] = wbTransfer.Byte.low;
00956
00957 wbTransfer.Word = fInPW(stg->wBaseAddress + CNT2_D);
00958
00959 lbEnc[2].Byte[i] = wbTransfer.Byte.high;
00960 lbEnc[3].Byte[i] = wbTransfer.Byte.low;
00961
00962 /* BUG FIX-- index rolls off end and kills stack if you
00963 have a 4 axis board after this point */
00964 if (stg->wAxesInSys < 8)
00965 {
00966 continue;
00967 }
00968
00969 wbTransfer.Word = fInPW(stg->wBaseAddress + CNT4_D);
00970
00971 lbEnc[4].Byte[i] = wbTransfer.Byte.high;
00972 lbEnc[5].Byte[i] = wbTransfer.Byte.low;
00973
00974 wbTransfer.Word = fInPW(stg->wBaseAddress + CNT6_D);
00975
00976 lbEnc[6].Byte[i] = wbTransfer.Byte.high;
00977 lbEnc[7].Byte[i] = wbTransfer.Byte.low;
00978 }
00979
00980 /* maintain the high byte, to extend the counter to 32 bits */
00981 /* */
00982 /* base decisions to increment or decrement the high byte */
00983 /* on the highest 2 bits of the 24 bit value. To get the */
00984 /* highest 2 bits, use 0xc0 as a mask on byte [2] (the third */
00985 /* byte). */
00986
00987 for (i = 0; i < MAX_AXIS; i++)
00988 {
00989 /* check for -1 to 0 transition */
00990
00991 if ( ( (stg->byOldByte2[i] & 0xc0) == 0xc0 ) /* 11xxxxxx */
00992 && ( (lbEnc[i].Byte[2] & 0xc0) == 0 ) /* 00xxxxxx */
00993 )
00994 stg->byEncHighByte[i]++;
00995
00996 /* check for 0 to -1 transition */
00997
00998 if ( ( (stg->byOldByte2[i] & 0xc0) == 0 ) /* 00xxxxxx */
00999 && ( (lbEnc[i].Byte[2] & 0xc0) == 0xc0 ) /* 11xxxxxx */
01000 )
01001 stg->byEncHighByte[i]--;
01002
01003 lbEnc[i].Byte[3] = stg->byEncHighByte[i];
01004 stg->byOldByte2[i] = lbEnc[i].Byte[2]; /* current byte 2 becomes old one */
01005 }
01006 };
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Definition at line 619 of file stg_v2_axis8.c. 00620 {
00621 unsigned short wAdd, uplim; /* for BUG FIX below */
00622 #if 0
00623 /* These variables are used only in the if 0'd out sections below. */
00624 unsigned short wA;
00625 unsigned short const wTestPat = 0x5aa5;
00626 LONGBYTE enc[MAX_AXIS]; /* BUG FIX-- was hard-coded 8 */
00627 #endif
00628
00629 if (stg->wNoBoardFlag == NO_BOARD)
00630 {
00631 stg->wAxesInSys = MAX_AXIS;
00632 return;
00633 }
00634
00635 /* It is possible that the encoder counts are being held by battery */
00636 /* backup, so we'll read the encoders, and save the values */
00637 /* Then we'll initialize the encoder chips, since it's more likely that */
00638 /* the ecoders were not kept alive by battery and need to be initialized */
00639
00640 #if 0
00641 /* FIXME-- we need to read all the encoders here, so temporarily set
00642 wAxesInSys to MAX_AXIS */
00643 stg->wAxesInSys = MAX_AXIS;
00644 EncReadAll(stg, enc);
00645 stg->wAxesInSys = 0;
00646 #endif
00647
00648 /* probably the right thing is to sign extend the 24 bits, so, instead */
00649 /* of a 24 bit unsigned count, we have +/- 23 bits. */
00650
00651 /* for ( i = 0; i < 8; i++) */
00652 /* { */
00653 /* byEncHighByte[i] = enc[i].Byte[2] & 0x80 ? 0xff : 0; */
00654 /* byOldByte2[i] = enc[i].Byte[2]; */
00655 /* } */
00656
00657 /* FIXME-- we don't yet have wAxesInSys, so we'll have to go to the max */
00658 uplim = stg->wBaseAddress + CNT6_C;
00659
00660 for (wAdd = stg->wBaseAddress + CNT0_C; wAdd <= uplim; wAdd +=4)
00661 {
00662 /* we're going to be slick and do two chips at a time, that's why */
00663 /* the registers are arranged data, data, control, control. You */
00664 /* can do two at a time, by using word operations, instead of */
00665 /* byte operations. Not a big deal for initializing, but reading is */
00666 /* done pretty often. */
00667
00668 fOutPW(wAdd, 0x2020); /* master reset */
00669
00670 /* Set Counter Command Register - Input Control, OL Load (P3), */
00671 /* and Enable Inputs A and B (INA/B). */
00672
00673 fOutPW(wAdd, 0x6868);
00674
00675 /* Set Counter Command Register - Output Control */
00676
00677 fOutPW(wAdd, 0x8080);
00678
00679 /* Set Co7unter Command Register - Quadrature */
00680
00681 fOutPW(wAdd, 0xc3c3);
00682
00683 fOutPW(wAdd, 0x0404); /* reset counter to zero */
00684 }
00685
00686 /* Figure out how many axes are on the card */
00687
00688 #if 0
00689 /* FIXME-- we don't yet have wAxesInSys, so we'll have to go to the max */
00690 uplim = stg->wBaseAddress + CNT6_D;
00691
00692 for (wA = stg->wBaseAddress + CNT0_D; wA <= uplim; wA +=4)
00693 {
00694 /* reset address pointer */
00695
00696 fOutPW(wA + 2, 0x0101);
00697
00698 /* write a pattern to the preset register */
00699
00700 fOutPW(wA, wTestPat);
00701 fOutPW(wA, wTestPat);
00702 fOutPW(wA, wTestPat);
00703
00704 /* transfer the preset register to the count register */
00705
00706 fOutPW(wA + 2, 0x0909);
00707
00708 /* transfer counter to output latch */
00709
00710 fOutPW(wA + 2, 0x0202);
00711
00712 /* read the output latch and see if it matches */
00713
00714 if (fInPW(wA) != wTestPat)
00715 break;
00716 if (fInPW(wA) != wTestPat)
00717 break;
00718 if (fInPW(wA) != wTestPat)
00719 break;
00720
00721 /* now replace the values that you saved previously, in case the */
00722 /* encoder was battery backed up */
00723
00724 fOutP(wA, enc[stg->wAxesInSys].Byte[0]);
00725 fOutP(wA, enc[stg->wAxesInSys].Byte[1]);
00726 fOutP(wA, enc[stg->wAxesInSys].Byte[2]);
00727
00728 fOutP(wA + 1, enc[stg->wAxesInSys + 1].Byte[0]);
00729 fOutP(wA + 1, enc[stg->wAxesInSys + 1].Byte[1]);
00730 fOutP(wA + 1, enc[stg->wAxesInSys + 1].Byte[2]);
00731
00732 /* transfer the preset register to the count register */
00733
00734 fOutPW(wA + 2, 0x0909);
00735
00736 stg->wAxesInSys += 2;
00737
00738 /* write zeros to preset register, we don't want to do a master reset */
00739 /* (MRST), because then we would need to re-initialize the counter */
00740
00741 /* fOutPW(wA, 0); */
00742 /* fOutPW(wA, 0); */
00743 /* fOutPW(wA, 0); */
00744
00745 /* reset counter, BRW and CRY and address pointer (RADR) */
00746
00747 /* fOutPW(wA + 2, 0x0505); */
00748 }
00749 #else
00750 stg->wAxesInSys = 8;
00751 #endif
00752 };
|
|
|
Definition at line 1447 of file stg_v2_axis8.c. 01448 {
01449 if (stg->wNoBoardFlag == NO_BOARD)
01450 {
01451 return;
01452 }
01453
01454 /* normally you'll have the timer latch the data in hardware, but */
01455 /* if the timer isn't running, we need to latch it ourselves. */
01456
01457 /* BUG FIX-- don't go past 4 axes on 4 axis board */
01458 fOutPW(stg->wBaseAddress + CNT0_C, 0x0303);
01459 fOutPW(stg->wBaseAddress + CNT2_C, 0x0303);
01460 if (stg->wAxesInSys > 4) {
01461 fOutPW(stg->wBaseAddress + CNT4_C, 0x0303);
01462 fOutPW(stg->wBaseAddress + CNT6_C, 0x0303);
01463 }
01464 };
|
|
|
Definition at line 1471 of file stg_v2_axis8.c. 01472 {
01473 if (stg->wNoBoardFlag == NO_BOARD)
01474 {
01475 return;
01476 }
01477
01478 /* This function resets all the counter's internal address pointers to point */
01479 /* to the first byte in the 3 byte sequence */
01480
01481 /* BUG FIX-- don't go past 4 axes on 4 axis board */
01482 fOutPW(stg->wBaseAddress + CNT0_C, 0x0101);
01483 fOutPW(stg->wBaseAddress + CNT2_C, 0x0101);
01484 if (stg->wAxesInSys > 4) {
01485 fOutPW(stg->wBaseAddress + CNT4_C, 0x0101);
01486 fOutPW(stg->wBaseAddress + CNT6_C, 0x0101);
01487 }
01488 };
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|
|
Definition at line 1539 of file stg_v2_axis8.c. 01540 {
01541 return stg->wBaseAddress;
01542 };
|
|
|
Definition at line 1529 of file stg_v2_axis8.c. 01530 {
01531 return stg->wAxesInSys;
01532 };
|
|
|
Definition at line 1519 of file stg_v2_axis8.c. 01520 {
01521 return fInP(stg->wBaseAddress + BRDTST);
01522 }
|
|
|
Definition at line 1524 of file stg_v2_axis8.c. 01525 {
01526 return stg->wNoBoardFlag;
01527 };
|
|
|
Definition at line 1500 of file stg_v2_axis8.c. 01501 {
01502 return fInP(stg->wBaseAddress + CNTRL0);
01503 }
|
|
|
Definition at line 1505 of file stg_v2_axis8.c. 01506 {
01507 return fInP(stg->wBaseAddress + CNTRL1);
01508 }
|
|
|
Definition at line 1495 of file stg_v2_axis8.c. 01496 {
01497 return fInP(stg->wBaseAddress + IDLEN);
01498 }
|
|
|
Definition at line 1112 of file stg_v2_axis8.c. 01113 {
01114 /* routine for Model 2 board */
01115
01116 return fInP(stg->wBaseAddress + IDL);
01117 }
|
|
|
Definition at line 1534 of file stg_v2_axis8.c. 01535 {
01536 return stg->wIrq;
01537 };
|
|
|
Definition at line 1544 of file stg_v2_axis8.c. 01545 {
01546 return stg->wModel;
01547 };
|
|
|
Definition at line 1490 of file stg_v2_axis8.c. 01491 {
01492 return fInP(stg->wBaseAddress + SELDI);
01493 }
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|
Definition at line 1554 of file stg_v2_axis8.c. 01555 {
01556 /* poll for the index pulse of the axis that was previously set up. */
01557 /* Normally you would look at the latched pulse. This function will */
01558 /* probably only get used during testing. */
01559
01560 unsigned char byIRR, byAxisMask;
01561
01562 byIRR = CurrentIRR(stg);
01563 byAxisMask = (stg->byIndexPollAxis & 1) ? IXODD : IXEVN; /* even or odd axis? */
01564
01565 /* The raw index pulse isn't inverted by the hardware if the index pulse is */
01566 /* low active (only the latched pulse is). For consistancy, we'll invert */
01567 /* the pulse in software. */
01568
01569 if (stg->byIndexPulsePolarity == 0) /* if pulse is low true */
01570 byIRR ^= byAxisMask; /* flip bit */
01571
01572 if (byIRR & byAxisMask) /* check index pulse */
01573 return 1;
01574 return 0;
01575 }
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|
Definition at line 1088 of file stg_v2_axis8.c. 01089 {
01090 /* routine for Model 1 board */
01091
01092 /* poll the latched index pulse of the axis that was previously set up */
01093
01094 unsigned char byIRR, byAxisMask;
01095
01096 byIRR = CurrentIRR(stg);
01097 byAxisMask = (stg->byIndexPollAxis & 1) ? LIXODD : LIXEVN; /* even or odd axis? */
01098 if (byIRR & byAxisMask) /* check latched index pulse */
01099 return 1;
01100 return 0;
01101
01102 /* */
01103 /* a faster, but messier way */
01104 /* */
01105 /*fOutP(stg->wBaseAddress + OCW3, 0x0a); // IRR on next read */
01106 /* */
01107 /*return ( fInP(stg->wBaseAddress + IRR) */
01108 /* & ( (stg->byIndexPollAxis & 1) ? LIXODD : LIXEVN ) // mask for even or odd */
01109 /* ); */
01110 }
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|
||||||||||||
|
Definition at line 416 of file stg_v2_axis8.c. 00417 {
00418 /*
00419 * First find the the base I/O address of the board.
00420 *
00421 * only do this in the DOS example. It's dangerous under 95, and can't be
00422 * done under NT
00423 */
00424 stg->wBaseAddress = BaseFind(stg);
00425 if (stg->wBaseAddress == 0)
00426 {
00427 stg->wNoBoardFlag = NO_BOARD;
00428 }
00429 else /* BUG FIX-- need an else */
00430 {
00431 stg->wNoBoardFlag = BOARD_PRESENT;
00432 }
00433 #ifndef rtlinux
00434 printf("Servo To Go Board IO address = 0x%X\n",stg->wBaseAddress);
00435 #endif
00436
00437 /*
00438 * Initialize the interrupt controller
00439 */
00440 if (stg->wModel == MODEL1)
00441 {
00442 fOutP(stg->wBaseAddress + MIO_2, 0x92); /* initialize INTC as output reg. */
00443 /* sets port D to input since we have */
00444 /* to set it to something. */
00445 SetIrq(stg, wRequestedIrq); /* selects the IRQ in INTC. Now, if a stray */
00446 /* interrupt is issued (see below) it will */
00447 /* go to an interrupt that isn't enabled on */
00448 /* the motherboard yet (if your system is */
00449 /* set up correctly). */
00450 fOutP(stg->wBaseAddress + ICW1, 0x1a ); /* initialize 82C59 as single chip, */
00451 /* level triggered */
00452 fOutP(stg->wBaseAddress + ICW2, 0x00 ); /* icw2 - not used, must write */
00453 /* could issue stray interrupt here - danger! */
00454 fOutP(stg->wBaseAddress + OCW1, 0xff); /* mask off all interrupt sources (the */
00455 /* interrupt on the motherboard isn't */
00456 /* enabled yet, you do that when you install */
00457 /* your interrupt handler.). */
00458 }
00459 else /* must be a Model 2 */
00460 {
00461 fOutP(stg->wBaseAddress + MIO_2, 0x8b); /* initialize CNTRL0 as output reg. */
00462 /* BRDTST to input. */
00463 /* sets port D, high and low, to input */
00464 /* since we have to set it to something. */
00465 SetIrq(stg, wRequestedIrq); /* selects the IRQ in CNTRL0. Now, if a stray */
00466 /* interrupt is issued (see below) it will */
00467 /* go to an interrupt that isn't enabled on */
00468 /* the motherboard yet (if your system is */
00469 /* set up correctly). */
00470 }
00471 };
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|
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Definition at line 1691 of file stg_v2_axis8.c. 01692 {
01693 if (stg->wNoBoardFlag == NO_BOARD)
01694 {
01695 return;
01696 }
01697
01698 if (stg->wModel == MODEL1)
01699 fOutP(stg->wBaseAddress + OCW1, CurrentIRR(stg) | TP2);
01700 else /* Model 2 */
01701 /* we want to save the state of the slave mode, and set the */
01702 /* high nibble bits high, so you don't reset any latches. */
01703 /* bit pattern: 1111x000 where x is don't change */
01704 fOutP(stg->wBaseAddress + CNTRL1,
01705 (fInP(stg->wBaseAddress + CNTRL1) & CNTRL1_NOT_SLAVE) | 0xf0);
01706 }
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Definition at line 1352 of file stg_v2_axis8.c. 01353 {
01354 static long lState_1[MAX_AXIS] = {0}; /* state variables */
01355 long lScaledUp;
01356 const short nScale = 10;
01357 int nAxis;
01358
01359 for (nAxis = 0; nAxis < MAX_AXIS; nAxis++)
01360 {
01361 /* The input is guaranteed to be +/- 12 bits */
01362 /* Scale up state so we don't loose resolution */
01363 lScaledUp = stg->lSimDac[nAxis] << nScale;
01364
01365 /* note: I assume right shift is sign preserving (for signed value) */
01366
01367 /* lag */
01368 lState_1[nAxis] += (lScaledUp - lState_1[nAxis]) >> (4 + nAxis); /*lint !e704 */
01369 /* ^^^^^^^ time constant */
01370 /* is different for each axis */
01371
01372 /* integrator (shift out the scale factor and then some) */
01373 stg->lSimEnc[nAxis] += lState_1[nAxis] >> (nScale + 1); /*lint !e704 */
01374 }
01375 }
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Definition at line 1654 of file stg_v2_axis8.c. 01655 {
01656 if (stg->wNoBoardFlag == NO_BOARD)
01657 {
01658 return 0;
01659 }
01660
01661 if (stg->wModel == MODEL1)
01662 return !(CurrentIRR(stg) & TP2); /* mask selects bit for TP2 */
01663 else /* MODEL 2 */
01664 {
01665 unsigned char byRegCntrl1, byNewCntrl1;
01666
01667 byRegCntrl1 = fInP(stg->wBaseAddress + CNTRL1);
01668 if (byRegCntrl1 & CNTRL1_INT_T2)
01669 {
01670 /* If it's set, we want to reset the latch, by writing a zero */
01671 /* to CNTRL1_INT_T2. */
01672
01673 /* When we write to CNTRL1, we don't want to change SLAVE, IEN_G2 */
01674 /* IEN_T2, or IEN_T0 -- the lower 4 bits. So, we start with */
01675
01676 byNewCntrl1 = byRegCntrl1 & 0x0f; /* (0000xxxx) */
01677
01678 /* We don't want to reset WDTOUT, INT_G2, or INT_T0--we only want */
01679 /* to reset ...T2. (1101xxxx) */
01680
01681 byNewCntrl1 |= CNTRL1_WDTOUT | CNTRL1_INT_G2 | CNTRL1_INT_T0;
01682
01683 fOutP(stg->wBaseAddress + CNTRL1, byNewCntrl1); /* reset bit */
01684
01685 return 1; /* true */
01686 }
01687 }
01688 return 0; /* false */
01689 }
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|
||||||||||||||||
|
Definition at line 863 of file stg_v2_axis8.c. 00864 {
00865 if (stg->wNoBoardFlag == NO_BOARD)
00866 {
00867 return;
00868 }
00869
00870 if ( nAxis > 7 ) /* is axis within range? */
00871 return;
00872
00873
00874 /* input / output: */
00875 /* */
00876 /* lCounts (decimal) ... -lCounts ... +0x1000 ... volts */
00877 /* */
00878 /* 0x1000 (4096) 0xfffff000 0 +10 */
00879 /*out 0 0 0x1000 0 */
00880 /* 0xfffff001 (-4095) 0xfff 0x1fff -10 */
00881
00882 /* So, the domain might be different than you expected. I expected: */
00883 /* 0xf000 (-4096) to 0xfff (4095), rather than */
00884 /* 0xf001 (-4095) to 0x1000 (4096) */
00885
00886 /* reverse slope so positive counts give positive voltage */
00887 lCounts = - lCounts;
00888
00889 /* shift for DAC */
00890 lCounts += 0x1000;
00891
00892 if (lCounts > 0x1FFF) /* clamp + output */
00893 {
00894 lCounts = 0x1FFF;
00895 }
00896 if (lCounts < 0) /* clamp - output */
00897 {
00898 lCounts = 0;
00899 }
00900
00901 if (stg->wNoBoardFlag == NO_BOARD) /* are we simulating? */
00902 {
00903 stg->lSimDac[nAxis] = lCounts;
00904 return;
00905 }
00906
00907 /* nCounts = (USHORT) (lCounts + 0x1000); // correct range for DAC */
00908
00909 fOutPW(stg->wBaseAddress + DAC_0 + (nAxis << 1), (unsigned short)lCounts);
00910 };
|
|
|
Definition at line 1125 of file stg_v2_axis8.c. 01126 {
01127 IO32 xInBits;
01128
01129 if (stg->wNoBoardFlag == NO_BOARD)
01130 {
01131 xInBits.all = 0;
01132 return(xInBits.all);
01133 }
01134
01135 if (stg->wModel == MODEL1)
01136 {
01137 xInBits.port.A = fInP(stg->wBaseAddress + DIO_A);
01138 xInBits.port.B = fInP(stg->wBaseAddress + DIO_B);
01139 xInBits.port.C = fInP(stg->wBaseAddress + DIO_C);
01140 xInBits.port.D = fInP(stg->wBaseAddress + DIO_D);
01141 }
01142 else /* Model 2 */
01143 {
01144 xInBits.port.A = fInP(stg->wBaseAddress + PORT_A);
01145 xInBits.port.B = fInP(stg->wBaseAddress + PORT_B);
01146 xInBits.port.C = fInP(stg->wBaseAddress + PORT_C);
01147 xInBits.port.D = fInP(stg->wBaseAddress + PORT_D);
01148 }
01149 return (xInBits.all);
01150 };
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|
||||||||||||
|
Definition at line 1158 of file stg_v2_axis8.c. 01159 {
01160 if (stg->wNoBoardFlag == NO_BOARD)
01161 {
01162 return;
01163 }
01164 if (stg->wModel == MODEL1)
01165 {
01166 fOutP(stg->wBaseAddress + DIO_A, ((IO32 *)&lOutBits)->port.A);
01167 fOutP(stg->wBaseAddress + DIO_B, ((IO32 *)&lOutBits)->port.B);
01168 fOutP(stg->wBaseAddress + DIO_C, ((IO32 *)&lOutBits)->port.C);
01169 fOutP(stg->wBaseAddress + DIO_D, ((IO32 *)&lOutBits)->port.D);
01170 }
01171 else /* Model 2 */
01172 {
01173 fOutP(stg->wBaseAddress + PORT_A, ((IO32 *)&lOutBits)->port.A);
01174 fOutP(stg->wBaseAddress + PORT_B, ((IO32 *)&lOutBits)->port.B);
01175 fOutP(stg->wBaseAddress + PORT_C, ((IO32 *)&lOutBits)->port.C);
01176 fOutP(stg->wBaseAddress + PORT_D, ((IO32 *)&lOutBits)->port.D);
01177 }
01178 };
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|
||||||||||||||||||||
|
Definition at line 1180 of file stg_v2_axis8.c. 01181 {
01182 unsigned nOffset;
01183 unsigned char byData;
01184
01185 if (stg->wNoBoardFlag == NO_BOARD)
01186 {
01187 return;
01188 }
01189
01190 if (nPort > 3)
01191 return;
01192
01193 if (stg->wModel == MODEL1)
01194 nOffset = aPortOffset_1[nPort];
01195 else /* Model 2 */
01196 nOffset = aPortOffset_2[nPort];
01197
01198 byData = fInP(stg->wBaseAddress + nOffset);
01199 if (bySet0or1 == 1)
01200 byData |= 1 << byBitNumber;
01201 else
01202 byData &= ~(1u << byBitNumber);
01203 fOutP(stg->wBaseAddress + nOffset, byData);
01204 };
|
|
||||||||||||||||
|
Definition at line 571 of file stg_v2_axis8.c. 00572 {
00573 if (stg->wNoBoardFlag == NO_BOARD)
00574 {
00575 return STG_SUCCESS;
00576 }
00577
00578 if (wAxis > 7)
00579 return STG_FAILURE;
00580
00581 if (stg->wModel == MODEL1)
00582 {
00583 if ( !(CurrentIRR(stg) & 0x08) ) /* is the conversion done? */
00584 return STG_FAILURE; /* no, return failure */
00585
00586 /* conversion is done, get counts. */
00587 /* *counts = fInPW(stg->wBaseAddress + ADC_0 + (wAxis << 1)); */
00588 /* *counts = fInPW(stg->wBaseAddress + ADC_1); // debug */
00589 }
00590 else /* Model 2 */
00591 {
00592 /* is the conversion done? */
00593 if ( fInP(stg->wBaseAddress + BRDTST) & BRDTST_EOC )
00594 return STG_FAILURE; /* no, return failure */
00595
00596 /* conversion is done, get counts. */
00597 /* *counts = fInPW(stg->wBaseAddress + ADC_1); */
00598 }
00599
00600 *counts = fInPW(stg->wBaseAddress + ADC_0 + (wAxis << 1));
00601
00602 if (*counts & 0x1000) /* is sign bit negative? */
00603 *counts |= 0xf000; /* sign extend */
00604 else
00605 *counts &= 0xfff; /* make sure high order bits are zero. */
00606
00607 return STG_SUCCESS;
00608
00609 };
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|
|
Definition at line 1644 of file stg_v2_axis8.c. 01645 {
01646 unsigned short count;
01647 char *pByte = (char *)&count;
01648 fOutP(stg->wBaseAddress + TMRCMD, 0x80); /* timer 2, latch */
01649 *pByte++ = fInP(stg->wBaseAddress + TIMER_2); /* LSB */
01650 *pByte = fInP(stg->wBaseAddress + TIMER_2); /* MSB */
01651 return count;
01652 }
|
|
|
Definition at line 1013 of file stg_v2_axis8.c. 01014 {
01015 /* routine for Model 1 */
01016
01017 fInP(stg->wBaseAddress + ODDRST); /*lint !e534 reset index pulse latch for ODD axis */
01018 fInP(stg->wBaseAddress + BRDTST); /*lint !e534 reset index pulse latch for EVEN axis */
01019 }
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|
||||||||||||
|
Definition at line 1021 of file stg_v2_axis8.c. 01022 {
01023 /* routine for Model 2 */
01024 fOutP(stg->wBaseAddress + IDL, byLatchBits);
01025 }
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|
|
Definition at line 1510 of file stg_v2_axis8.c. 01511 {
01512 unsigned char byCntrl1 = fInP(stg->wBaseAddress + CNTRL1);
01513 byCntrl1 &= ~CNTRL1_WDTOUT; /*set bit low, to reset */
01514 /* don't reset other latches */
01515 byCntrl1 |= CNTRL1_INT_G2 | CNTRL1_INT_T2 | CNTRL1_INT_T0;
01516 fOutP(stg->wBaseAddress + CNTRL1, byCntrl1);
01517 }
|
|
||||||||||||||||
|
Definition at line 1033 of file stg_v2_axis8.c. 01034 {
01035 /* routine for Model 1 */
01036
01037 /* */
01038 /* initialize stuff to poll index pulse */
01039 /* */
01040 unsigned char byIntc;
01041
01042 stg->byIndexPollAxis = byAxis; /* save axis to check later */
01043 stg->byIndexPulsePolarity = byPol; /* save polarity as new default */
01044 byAxis &= 0x6; /* ignore low bit, we check 2 axes at a time */
01045 byAxis <<= 3; /* shift into position for IXS1, IXS0 */
01046 byIntc = fInP(stg->wBaseAddress + INTC); /* get a copy of INTC, we'll change */
01047 /* some bits in it, not all */
01048 byIntc &= ~(IXLVL | IXS1 | IXS0); /* zero bits for axis and polarity */
01049 byIntc |= byAxis; /* put axes address in INTC */
01050 if (byPol != 0) /* is index pulse active high? */
01051 byIntc |= IXLVL;
01052 fOutP(stg->wBaseAddress + INTC, byIntc);
01053 ResetIndexLatch(stg);
01054
01055 /* The latched index pulse should be low now. If it's not, either something's */
01056 /* wrong, or we happened to initialize it while the index pulse was active. */
01057 }
|
|
||||||||||||
|
Definition at line 1059 of file stg_v2_axis8.c. 01060 {
01061 /* routine for Model 2 */
01062
01063 fOutP(stg->wBaseAddress + SELDI, bySelectBits);
01064 }
|
|
||||||||||||
|
Definition at line 759 of file stg_v2_axis8.c. 00760 {
00761 if (stg->wNoBoardFlag == NO_BOARD)
00762 {
00763 return;
00764 }
00765
00766 if (lPeriodSelect != MAX_PERIOD)
00767 {
00768 fOutP(stg->wBaseAddress + TMRCMD, 0x56); /* timer 1, read/load LSB (MSB is 0) */
00769 /* mode 3 (square wave) */
00770 fOutP(stg->wBaseAddress + TIMER_1, 0xb4); /* 0xb4 = 180 -> 25 uSec period */
00771 }
00772 else
00773 {
00774 fOutP(stg->wBaseAddress + TMRCMD, 0x76); /* timer 1, read/load LSB then MSB */
00775 /* mode 3 (square wave) */
00776 fOutP(stg->wBaseAddress + TIMER_1, 0xff); /* LSB */
00777 fOutP(stg->wBaseAddress + TIMER_1, 0xff); /* MSB */
00778 }
00779
00780 switch (lPeriodSelect)
00781 {
00782 case _500_MICROSECONDS:
00783 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00784 /* MSB, mode 2 (real-time interrupt) */
00785 fOutP(stg->wBaseAddress + TIMER_0, 0x14); /* 0x14 = 20 = .5 mS */
00786 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00787 break;
00788 case _1_MILLISECOND:
00789 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00790 /* MSB, mode 2 (real-time interrupt) */
00791 fOutP(stg->wBaseAddress + TIMER_0, 0x28); /* 0x28 = 40 = 1 mS */
00792 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00793 break;
00794 case _2_MILLISECONDS:
00795 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00796 /* MSB, mode 2 (real-time interrupt) */
00797 fOutP(stg->wBaseAddress + TIMER_0, 0x50); /* 0x50 = 80 = 2 mS */
00798 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00799 break;
00800 case _3_MILLISECONDS:
00801 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00802 /* MSB, mode 2 (real-time interrupt) */
00803 fOutP(stg->wBaseAddress + TIMER_0, 0x78); /* 0x78 = 120 = 3 mS */
00804 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00805 break;
00806 case _4_MILLISECONDS:
00807 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00808 /* MSB, mode 2 (real-time interrupt) */
00809 fOutP(stg->wBaseAddress + TIMER_0, 0xA0); /* 0xA0 = 160 = 4 mS */
00810 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00811 break;
00812 case _5_MILLISECONDS:
00813 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00814 /* MSB, mode 2 (real-time interrupt) */
00815 fOutP(stg->wBaseAddress + TIMER_0, 0xC8); /* 0xC8 = 200 = 5 mS */
00816 fOutP(stg->wBaseAddress + TIMER_0, 0x00);
00817 break;
00818 case _10_MILLISECONDS:
00819 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00820 /* MSB, mode 2 (real-time interrupt) */
00821 fOutP(stg->wBaseAddress + TIMER_0, 0x90); /* 0x0190 = 400 = 10 mS */
00822 fOutP(stg->wBaseAddress + TIMER_0, 0x01);
00823 break;
00824 case _100_MILLISECONDS:
00825 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00826 /* MSB, mode 2 (real-time interrupt) */
00827 fOutP(stg->wBaseAddress + TIMER_0, 0xA0); /* 0x0FA0 = 4000 = 100 mS */
00828 fOutP(stg->wBaseAddress + TIMER_0, 0x0F);
00829 break;
00830 case _1_SECOND:
00831 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00832 /* MSB, mode 2 (real-time interrupt) */
00833 fOutP(stg->wBaseAddress + TIMER_0, 0x40); /* 0x9C40 = 40000 = 1 S */
00834 fOutP(stg->wBaseAddress + TIMER_0, 0x9c);
00835 break;
00836 case MAX_PERIOD:
00837 fOutP(stg->wBaseAddress + TMRCMD, 0x34); /* timer 0, read/load LSB followed by */
00838 /* MSB, mode 2 (real-time interrupt) */
00839 fOutP(stg->wBaseAddress + TIMER_0, 0xff); /* LSB */
00840 fOutP(stg->wBaseAddress + TIMER_0, 0xff); /* MSB */
00841 break;
00842 default:
00843 /* wrong input? then don't change it */
00844 break;
00845 }
00846 };
|
|
||||||||||||
|
Definition at line 236 of file stg_v2_axis8.c. 00237 {
00238 int t;
00239
00240 #if defined (LINUX)
00241 iopl(3); /* get access to I/O ports, must be root. */
00242 #endif
00243
00244 /* BUG FIX-- init globals */
00245 stg->wAxesInSys = 0;
00246 stg->wBaseAddress = 0;
00247 stg->wIrq = 0;
00248 stg->wModel = MODEL_NO_ID;
00249 stg->wNoBoardFlag = NO_BOARD;
00250 stg->wAxesInSys = 0;
00251 stg->wSaveDirs = 0;
00252 stg->byIndexPollAxis = 0;
00253 stg->byIndexPulsePolarity = 1;
00254 for (t = 0; t < MAX_AXIS; t++) {
00255 stg->lSimDac[t] = 0;
00256 stg->lSimEnc[t] = 0;
00257 stg->byEncHighByte[t] = 0;
00258 stg->byOldByte2[t] = 0;
00259 }
00260
00261 Initialize(stg, wRequestedIrq); /* figure out board address, init irq controller */
00262 EncoderInit(stg);
00263 SelectInterruptPeriod(stg, _1_MILLISECOND); /* initialize timer */
00264 stg->byIndexPulsePolarity = 1; /* default active level high */
00265 if (stg->wModel == MODEL2)
00266 fOutP(stg->wBaseAddress + CNTRL1, CNTRL1_NOT_SLAVE);
00267 };
|
|
|
Definition at line 274 of file stg_v2_axis8.c. 00275 {
00276 unsigned short nAxis;
00277
00278 StopInterrupts(stg);
00279
00280 /* set all the DAC outputs to 0. */
00281 for (nAxis = 0; nAxis < MAX_AXIS; nAxis++)
00282 RawDAC(stg, nAxis, 0);
00283
00284 /* set all the digital I/O bits to input */
00285 DioDirection(stg, 0);
00286 }
|
|
||||||||||||
|
Definition at line 1289 of file stg_v2_axis8.c. 01290 {
01291 unsigned char byHwDir; /* direction bits for hardware */
01292 unsigned char bySaveReg, bySaveIMR, bySaveCntrl1, bySaveCntrl0;
01293
01294 if (stg->wModel == MODEL1)
01295 {
01296 bySaveReg = fInP(stg->wBaseAddress + INTC); /* INTC needs to be saved, because */
01297 /* MIO_2 reinitializes the 8255 which */
01298 /* implements the INTC register. */
01299 byHwDir = 0x92; /* initialize port D input */
01300 if (nSwDir & STG_PORT_D) /* is port D output? */
01301 byHwDir &= ~D_DIR_BIT; /* if yes, set bit to 0, */
01302 bySaveIMR = fInP(stg->wBaseAddress + IMR); /* get the current interrupt mask */
01303 fOutP(stg->wBaseAddress + OCW1, 0xff); /* mask off all interrupts */
01304 fOutP(stg->wBaseAddress + MIO_2, byHwDir); /* set direction for port D */
01305 fOutP(stg->wBaseAddress + INTC, bySaveReg); /* restore interrupt control reg. */
01306 fOutP(stg->wBaseAddress + OCW1, bySaveIMR); /* restore interrupt mask */
01307 }
01308 else /* Model 2 */
01309 {
01310 bySaveCntrl0 = fInP(stg->wBaseAddress + CNTRL0); /* CNTRL0 needs to be saved, because */
01311 /* D_DIR reinitializes the 8255 which */
01312 /* implements the CNTRL0 register. */
01313 byHwDir = 0x8b; /* initialize CNTRL0 as output reg. */
01314 /* BRDTST to input. */
01315 /* sets port D, high and low, to input */
01316 if (nSwDir & STG_PORT_D_LO) /* low nibble */
01317 byHwDir &= ~D_LOW_DIR_BIT;
01318 if (nSwDir & STG_PORT_D_HI) /* high nibble */
01319 byHwDir &= ~D_HI_DIR_BIT;
01320
01321 bySaveCntrl1 = fInP(stg->wBaseAddress+CNTRL1);/* save for interrupt enables */
01322
01323 /* don't reset any latches; put in slave state; */
01324 /* disable interrupts, so the glitch in CTRL0 doesn't */
01325 /* cause an interrupt on wrong irq */
01326 fOutP(stg->wBaseAddress + CNTRL1, 0xf0);
01327
01328 fOutP(stg->wBaseAddress + D_DIR, byHwDir); /* set port D direction */
01329
01330 /* restore CNTRL0, because it was re-initialized, which */
01331 /* lost any previous contents. */
01332 fOutP(stg->wBaseAddress + CNTRL0, bySaveCntrl0);
01333
01334 /* re-enable interrupts, and restore slave state, don't */
01335 /* reset any latches. (1111xxxx) */
01336 fOutP(stg->wBaseAddress+CNTRL1, (bySaveCntrl1 & 0x0f) | 0xf0);
01337 }
01338 };
|
|
||||||||||||||||
|
Definition at line 1418 of file stg_v2_axis8.c. 01419 {
01420 unsigned short wAddress;
01421 char *ByteUnion = (char *)&lCounts; /* get pointer to lCounts, so you */
01422 /* can take it apart byte by byte */
01423
01424 wAddress = stg->wBaseAddress + CNT0_D;
01425 wAddress += (nAxis & 0x6) << 1; /* shift to multiply by 2 */
01426 /* pairs of data regs seperated by pairs */
01427 /* of control regs, skip over control. */
01428 wAddress += nAxis & 1;
01429 fOutP(wAddress, ByteUnion[0]);
01430 fOutP(wAddress, ByteUnion[1]);
01431 fOutP(wAddress, ByteUnion[2]);
01432
01433 /* transfer the preset register to the count register */
01434 fOutP(wAddress + 2, 0x09);
01435
01436 /* set things for the part that extends the 24 bit counter */
01437 /* to 32 bits. */
01438 stg->byEncHighByte[nAxis] = ByteUnion[3];
01439 stg->byOldByte2[nAxis] = ByteUnion[2];
01440 }
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|
||||||||||||
|
Definition at line 293 of file stg_v2_axis8.c. 00294 {
00295 unsigned char byIntReg;
00296
00297 if (stg->wNoBoardFlag == NO_BOARD)
00298 return;
00299
00300 stg->wIrq = wRequestedIrq; /* assume it's OK for now, check later */
00301
00302 if (stg->wModel == MODEL1)
00303 byIntReg = 0x80; /* initial value for the high bits in the register */
00304 /* sets auto zero off */
00305 else /* MODEL2 */
00306 byIntReg = 0x88; /* cal high too, not calibrating ADC */
00307
00308 /* now put low bits into byIntReg to select irq */
00309
00310 switch (wRequestedIrq)
00311 {
00312 case 3: break; /* add zero */
00313
00314 case 5: byIntReg |= 4;
00315 break;
00316
00317 case 7: byIntReg |= 2;
00318 break;
00319
00320 case 9: byIntReg |= 6;
00321 break;
00322
00323 case 10: byIntReg |= 5;
00324 break;
00325
00326 case 11: byIntReg |= 7;
00327 break;
00328
00329 case 12: byIntReg |= 3;
00330 break;
00331
00332 case 15: byIntReg |= 1;
00333 break;
00334
00335 default: stg->wIrq = 5; /* ERROR, requested irq not valid, use 5 */
00336 byIntReg |= 4; /* There is no safe value, leaving zero */
00337 /* here would select IRQ 3 which is worse */
00338 /* than 5 because IRQ 3 is usually for COM 2 */
00339 break;
00340 }
00341
00342 if (stg->wModel == MODEL1)
00343 fOutP(stg->wBaseAddress + INTC, byIntReg); /* set irq */
00344 else /* MODEL2 */
00345 fOutP(stg->wBaseAddress + CNTRL0, byIntReg);
00346 }
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|
||||||||||||
|
Definition at line 530 of file stg_v2_axis8.c. 00531 {
00532 short counts;
00533 short j;
00534
00535 if (stg->wNoBoardFlag == NO_BOARD)
00536 {
00537 return 0;
00538 }
00539
00540 if (wAxis > 7)
00541 return -1;
00542
00543 if (stg->wModel == MODEL1)
00544 {
00545 /* make sure conversion is done, assume polling delay is done. */
00546 /* EOC (End Of Conversion) is bit 0x08 in IIR (Interrupt Request */
00547 /* Register) of Interrupt Controller. Don't wait forever though */
00548 /* bail out eventually. */
00549
00550 for (j = 0; (!(CurrentIRR(stg) & 0x08)) && (j < 10000); j++);
00551
00552 counts = ( fInPW(stg->wBaseAddress + ADC_0 + (wAxis << 1)) );
00553 }
00554 else
00555 {
00556 /* is the conversion done? */
00557 for (j = 0; (fInP(stg->wBaseAddress + BRDTST) & BRDTST_EOC) && (j < 10000); j++);
00558
00559 /* conversion is done, get counts. */
00560 counts = fInPW(stg->wBaseAddress + ADC);
00561 }
00562
00563 if (counts & 0x1000) /* is sign bit negative? */
00564 counts |= 0xf000; /* sign extend */
00565 else
00566 counts &= 0xfff; /* make sure high order bits are zero. */
00567
00568 return counts;
00569 };
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|
||||||||||||
|
Definition at line 478 of file stg_v2_axis8.c. 00479 {
00480 unsigned char Cntrl0;
00481
00482 if (stg->wNoBoardFlag == NO_BOARD)
00483 {
00484 return;
00485 }
00486
00487 if (wAxis > 7)
00488 return;
00489
00490 if (stg->wModel == MODEL1)
00491 {
00492 /* do a dummy read from the ADC, just to set the input multiplexer to */
00493 /* the right channel */
00494 fInPW(stg->wBaseAddress + ADC_0 + (wAxis << 1)); /*lint !e534 */
00495
00496 /* wait 4 uS for settling time on the multiplexer and ADC */
00497 /* you probably shouldn't really have a delay in */
00498 /* a driver. */
00499 Timer2Delay(stg, 28);
00500
00501 /* now start conversion. */
00502 fOutPW(stg->wBaseAddress + ADC_0 + (wAxis << 1), 0);
00503 }
00504 else /* Model 2 */
00505 {
00506 Cntrl0 = fInP(stg->wBaseAddress + CNTRL0) & 0x07; /* save irq */
00507
00508 Cntrl0 |= (wAxis << 4) | 0x88; /* shift bits to AD2, AD1, AD0 */
00509 /* set bit 0x80 high for autozero */
00510 /* set bit 0x08 high, not calibrating */
00511 fOutP(stg->wBaseAddress + CNTRL0, Cntrl0); /* select ADC channel */
00512
00513 /* don't have to do a dummy read for a model 2 */
00514
00515 /* wait 4 uS for settling time on the multiplexer and ADC */
00516 /* you probably shouldn't really have a delay in */
00517 /* a driver. */
00518 Timer2Delay(stg, 28);
00519
00520 /* now start conversion. */
00521 fOutPW(stg->wBaseAddress + ADC, 0);
00522 }
00523 };
|
|
|
Definition at line 1727 of file stg_v2_axis8.c. 01728 {
01729 if (stg->wNoBoardFlag == NO_BOARD)
01730 {
01731 return;
01732 }
01733 if (stg->wModel == MODEL1)
01734 fOutP(stg->wBaseAddress + OCW1, ~0x04); /* enable interrupt for timer 0 */
01735 else /* MODEL2 */
01736 /* we want to save the state of the slave mode, and set the */
01737 /* high nibble bits high, so you don't reset any latches. */
01738 /* 1111x001, where x means don't change */
01739 {
01740 fOutP(stg->wBaseAddress + CNTRL1, CNTRL1_IEN_T0 | CNTRL1_NOT_SLAVE);
01741 }
01742 };
|
|
||||||||||||
|
Definition at line 1629 of file stg_v2_axis8.c. 01630 {
01631 char *pByte = (char *)&count;
01632
01633 if (stg->wNoBoardFlag == NO_BOARD)
01634 {
01635 return;
01636 }
01637
01638 fOutP(stg->wBaseAddress + TMRCMD, 0xb4); /* timer 2, read/load LSB followed */
01639 /* by MSB, mode 2 (real time int). */
01640 fOutP(stg->wBaseAddress + TIMER_2, *pByte++); /* LSB (little endian) */
01641 fOutP(stg->wBaseAddress + TIMER_2, *pByte); /* MSB */
01642 }
|
|
||||||||||||
|
Definition at line 1614 of file stg_v2_axis8.c. 01615 {
01616 char *pByte = (char *)&count;
01617
01618 if (stg->wNoBoardFlag == NO_BOARD)
01619 {
01620 return;
01621 }
01622
01623 fOutP(stg->wBaseAddress + TMRCMD, 0xb0); /* timer 2, read/load LSB followed */
01624 /* by MSB, mode 0 (terminal count) */
01625 fOutP(stg->wBaseAddress + TIMER_2, *pByte++); /* LSB (little endian) */
01626 fOutP(stg->wBaseAddress + TIMER_2, *pByte); /* MSB */
01627 }
|
|
|
Definition at line 1749 of file stg_v2_axis8.c. 01750 {
01751 if (stg->wNoBoardFlag == NO_BOARD)
01752 {
01753 return;
01754 }
01755 if (stg->wModel == MODEL1)
01756 fOutP(stg->wBaseAddress + OCW1, 0xff); /* disable all interrupts */
01757 else /* MODEL2 */
01758 /* we want to save the state of the slave mode, and set the */
01759 /* high nibble bits high, so you don't reset any latches. */
01760 /* disable all interrupts, since only one can be enabled at */
01761 /* a time (currently). If more than one was enabled, it's */
01762 /* an error (currently). */
01763 /* 1111x000, where x means not changed. */
01764 fOutP(stg->wBaseAddress + CNTRL1,
01765 (fInP(stg->wBaseAddress + CNTRL1) & CNTRL1_NOT_SLAVE) | 0xf0);
01766 };
|
|
|
Definition at line 1582 of file stg_v2_axis8.c. 01583 {
01584 if (stg->wNoBoardFlag == NO_BOARD)
01585 {
01586 return;
01587 }
01588
01589 /* stop the timer by putting it into one shot mode, it will never get */
01590 /* a trigger */
01591
01592 /* bug bug this doesn't work */
01593
01594 fOutP(stg->wBaseAddress + TMRCMD, 0x0a); /* timer 0, mode 1 */
01595 }
|
|
||||||||||||
|
Definition at line 1602 of file stg_v2_axis8.c. 01603 {
01604 if (stg->wNoBoardFlag == NO_BOARD)
01605 {
01606 return;
01607 }
01608
01609 StartTimer2TerminalCount(stg, counts);
01610
01611 while (PollTimer2(stg));
01612 }
|
|
|
Definition at line 1708 of file stg_v2_axis8.c. 01709 {
01710 if (stg->wModel == MODEL1)
01711 fOutP(stg->wBaseAddress + OCW1, CurrentIRR(stg) & ~TP2);
01712 else /* Model 2 */
01713 {
01714 /* we want to save the state of the slave mode, and set the */
01715 /* high nibble bits high, so you don't reset any latches. */
01716 /* bit pattern: 1111x010 where x is don't change */
01717 fOutP(stg->wBaseAddress + CNTRL1,
01718 (fInP(stg->wBaseAddress + CNTRL1) & CNTRL1_NOT_SLAVE) | CNTRL1_IEN_T2);
01719 }
01720 }
|
|
|
Definition at line 25 of file stg2.h. 00025 : stg2.h,v 1.5 2001/10/30 23:34:05 paul_c Exp $";
00026
00027 /*
00028 Number of axes in system defaults to 4. If STG_8_AXES is defined
00029 by compiler directive or other means, code will support 8 axes,
00030 e.g., -DSTG_8_AXES. Note that only 6 axes are really supported, since
00031 there is not enough digital IO for limit and home switches for all 8.
00032
00033 Analog input is an option, normally not present. If STG_ANALOG_INPUT is
00034 defined by compiler directive or other means, code will support analog
00035 input, e.g., -DSTG_ANALOG_INPUT
00036 */
00037
00038 /*
00039 Base address defaults to 0x200
00040 */
00041 #define DEFAULT_STG_BASE_ADDRESS 0x200
00042 extern unsigned short STG_BASE_ADDRESS;
00043
00044 /* decls for external interface */
00045
00046 extern int stgMotInit(const char * stuff);
00047 extern int stgMotQuit(void);
00048
00049 extern int stgDacNum(void);
00050 extern int stgDacWrite(int dac, double volts);
00051 extern int stgDacWriteAll(int max, double * volts);
00052
00053 extern int stgEncoderSetIndexModel(unsigned int model);
00054 extern int stgEncoderNum(void);
00055 extern int stgEncoderRead(int encoder, double * counts);
00056 extern int stgEncoderReadAll(int max, double * counts);
00057 extern int stgEncoderResetIndex(int encoder);
00058 extern int stgEncoderReadLatch(int encoder, int * flag);
00059 extern int stgEncoderReadLevel(int encoder, int * flag);
00060
00061 extern int stgMaxLimitSwitchRead(int axis, int * flag);
00062 extern int stgMinLimitSwitchRead(int axis, int * flag);
00063
00064 extern int stgHomeSwitchRead(int axis, int * flag);
00065
00066 extern int stgAmpEnable(int axis, int enable);
00067 extern int stgAmpFault(int axis, int * fault);
00068
00069 extern int stgDioInit(const char * stuff);
00070 extern int stgDioQuit(void);
00071
00072 extern int stgDioMaxInputs(void);
00073 extern int stgDioMaxOutputs(void);
00074 extern int stgDioRead(int index, int *value);
00075 extern int stgDioWrite(int index, int value);
00076 extern int stgDioCheck(int index, int *value);
00077 extern int stgDioByteRead(int index, unsigned char *byte);
00078 extern int stgDioShortRead(int index, unsigned short *sh);
00079 extern int stgDioWordRead(int index, unsigned int *word);
00080 extern int stgDioByteWrite(int index, unsigned char byte);
00081 extern int stgDioShortWrite(int index, unsigned short sh);
00082 extern int stgDioWordWrite(int index, unsigned int word);
00083 extern int stgDioByteCheck(int index, unsigned char *byte);
00084 extern int stgDioShortCheck(int index, unsigned short *sh);
00085 extern int stgDioWordCheck(int index, unsigned int *word);
00086
00087 extern int stgAioInit(const char * stuff);
00088 extern int stgAioQuit(void);
00089
00090 extern int stgAioMaxInputs(void);
00091 extern int stgAioMaxOutputs(void);
00092 extern int stgAioStart(int index);
00093 extern void stgAioWait(void);
00094 extern int stgAioRead(int index, double *volts);
00095 extern int stgAioWrite(int index, double volts);
00096 extern int stgAioCheck(int index, double *volts);
00097 extern int stgModel(void);
00098
00099 #define STG_SUCCESS 0
00100 #define STG_FAILURE 1
00101
00102 #define NUM_AXIS_IN_SYS 8
00103 #define MAX_AXIS 8
00104
00105 #define CNT0_D 0x00
00106 #define CNT1_D 0x01
00107 #define CNT0_C 0x02
00108 #define CNT1_C 0x03
00109 #define CNT2_D 0x04
00110 #define CNT3_D 0x05
00111 #define CNT2_C 0x06
00112 #define CNT3_C 0x07
00113 #define CNT4_D 0x08
00114 #define CNT5_D 0x09
00115 #define CNT4_C 0x0a
00116 #define CNT5_C 0x0b
00117 #define CNT6_D 0x0c
00118 #define CNT7_D 0x0d
00119 #define CNT6_C 0x0e
00120 #define CNT7_C 0x0f
00121 #define DAC_0 0x10
00122 #define DAC_1 0x12
00123 #define DAC_2 0x14
00124 #define DAC_3 0x16
00125 #define DAC_4 0x18
00126 #define DAC_5 0x1a
00127 #define DAC_6 0x1c
00128 #define DAC_7 0x1e
00129 #define ADC 0x410
00130 #define ADC_0 0x410
00131 #define ADC_1 0x412
00132 #define ADC_2 0x414
00133 #define ADC_3 0x416
00134 #define ADC_4 0x418
00135 #define ADC_5 0x41a
00136 #define ADC_6 0x41c
00137 #define ADC_7 0x41e
00138 #define CNTRL0 0x401 /* Model 2 */
00139 #define DIO_A 0x400 /* Model 1 */
00140 #define DIO_B 0x402 /* Model 1 */
00141 #define DIO_C 0x404 /* Model 1 */
00142 #define DIO_D 0x401 /* Model 1 */
00143 #define PORT_A 0x400 /* Model 2, replaces DIO_A */
00144 #define PORT_B 0x402 /* Model 2, replaces DIO_B */
00145 #define PORT_C 0x404 /* Model 2, replaces DIO_C */
00146 #define PORT_D 0x405 /* Model 2, replaces DIO_D */
00147 #define INTC 0x405 /* Model 1 */
00148 #define BRDTST 0x403
00149 #define MIO_1 0x406
00150 #define ABC_DIR 0x406 /* Model 2 */
00151 #define MIO_2 0x407
00152 #define D_DIR 0x407 /* Model 2 */
00153 #define ODDRST 0x407
00154 #define TIMER_0 0x408
00155 #define TIMER_1 0x40a
00156 #define TIMER_2 0x40c
00157 #define TMRCMD 0x40e
00158 #define ICW1 0x409
00159 #define ICW2 0x40b
00160 #define OCW1 0x40b
00161 #define OCW2 0x409
00162 #define OCW3 0x409
00163 #define IRRreg 0x409 /* there's something called IRR in ntddk.h */
00164 #define ISR 0x409
00165 #define IDLEN 0x409
00166 #define IMR 0x40b
00167 #define SELDI 0x40b
00168 #define IDL 0x40d
00169 #define CNTRL1 0x40f
00170
00171 /*
00172 * Some bit masks for various registers
00173 */
00174 /* for IRR, ISR, and IMR */
00175 #define IXEVN 0x80
00176 #define IXODD 0x40
00177 #define LIXEVN 0x20
00178 #define LIXODD 0x10
00179 #define EOC 0x08
00180 #define TP0 0x04
00181 #define USR_INT 0x02
00182 #define TP2 0x01
00183 /* for INTC */
00184 #define AUTOZERO 0x80
00185 #define IXLVL 0x40
00186 #define IXS1 0x20
00187 #define IXS0 0x10
00188 #define USRINT 0x08
00189 #define IA2 0x04
00190 #define IA1 0x02
00191 #define IA0 0x01
00192
00193 #define CNTRL0_AZ 0x80
00194 #define CNTRL0_AD2 0x40
00195 #define CNTRL0_AD1 0x20
00196 #define CNTRL0_AD0 0x10
00197 #define CNTRL0_CAL 0x08
00198 #define CNTRL0_IA2 0x04
00199 #define CNTRL0_IA1 0x02
00200 #define CNTRL0_IA0 0x01
00201
00202 #define CNTRL1_WDTOUT 0x80
00203 #define CNTRL1_INT_G2 0x40
00204 #define CNTRL1_INT_T0 0x10
00205 #define CNTRL1_INT_T2 0x20
00206 #define CNTRL1_NOT_SLAVE 0x08
00207 #define CNTRL1_IEN_G2 0x04
00208 #define CNTRL1_IEN_T0 0x01
00209 #define CNTRL1_IEN_T2 0x02
00210
00211 #define BRDTST_EOC 0x08
00212
00213 /*
00214 * We're hardwired to irq 5 (sorry). This is normally reserved for
00215 * lpt2, but most people don't have two printers. Sometimes a modem,
00216 * sound card, etc. will be using this interrupt. It would be easiest
00217 * to remove any offending card temporarily. Otherwise you'll have
00218 * to figure out how to change the following define's.
00219 */
00220 #define INTR 13 /* irq5 is short 13 */
00221 #define INT_MASK 0x20 /* mask for motherboard interrupt controller */
00222 #define IC_ADD 0x20 /* address of the interrupt controller on your */
00223 /* motherboard (NOT the one on the Servo To Go */
00224 /* board). For low numbered interrupts (0-7) */
00225 /* it's 0x20, for higher numbered interrupts */
00226 /* (8-15) it's 0xa0 */
00227 #define EOI_5 0x65 /* Specific EOI for IRQ 5 (used with above) */
00228 #define IC_MASK 0x21 /* The interrupt mask register on your motherboard */
00229
00230 #define IRQSL 0x84 /* IRQ selection for INTC register */
00231 /* end of irq related defines */
00232
00233 /* */
00234 /* digital I/O port stuff */
00235 /* */
00236 /* begin to use the enumerated type, rather than the defines */
00237 /* */
00238 typedef enum { A_dir = 0x01, B_dir = 0x02, C_lo_dir = 0x04,
00239 C_hi_dir = 0x08, C_dir = 0x0c, D_lo_dir = 0x10,
00240 D_hiDir = 0x20, D_dir = 0x30 } eDir_typ;
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1.2.11.1 written by Dimitri van Heesch,
© 1997-2001